Methods of fabricating three-dimensional semiconductor memory devices using direct strapping line connections

ABSTRACT

Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.13/543,312, filed Jul. 6, 2012 in the United States Patent and TrademarkOffice and claims the benefit of Korean Patent Application No.10-2011-0067478, filed on Jul. 7, 2011, in the Korean IntellectualProperty Office, the disclosures of which are incorporated by referenceherein in their entireties.

BACKGROUND OF THE INVENTION

Embodiments of the subject matter relate generally to semiconductordevices and, more particularly, to three-dimensional semiconductormemory devices and methods of fabricating the same.

Due to their small size, multifunctional capabilities and/or low cost,semiconductor devices are important elements in the electronic industry.Higher integration of semiconductor devices is desired to satisfyconsumer demands for superior performance and lower cost. In the case ofsemiconductor memory devices, since their integration is an importantfactor in determining product prices, increased integration isespecially desirable,

In typical two-dimensional or planar semiconductor memory devices, thedegree of integration is generally limited by the area occupied by aunit memory cell, which may be limited by fine pattern formingtechnology. In particular, the expense of process equipment needed toincrease pattern fineness may act as a practical limitation onincreasing integration for two-dimensional or planar semiconductormemory devices. To overcome such a limitation, there have been recentlyproposed three-dimensional semiconductor memory devices having multiplelayers of memory cells.

SUMMARY

Some embodiments of inventive subject matter provide memory devicesincluding a plurality of elongate gate stacks extending in parallel on asubstrate, at least one insulation region disposed in a trench betweenadjacent ones of the gate stacks, the at least one insulation regionhaving linear first portions having a first width and widened secondportions having a second width greater than the first width. A commonsource region is disposed in the substrate underlying the at least oneinsulation region. The devices further include respective conductiveplugs passing through respective ones of the widened second portions ofthe at least one insulation region and electrically connected to thecommon source region and at least one strapping line disposed on theconductive plugs between the adjacent ones of the gate stacks and indirect contact with the conductive plugs.

In further embodiments, each of the gate stacks may include a pluralityof vertical channel regions distributed along a first direction. Theplugs may be spaced apart along the first direction. The at least onestrapping line may extend along the first horizontal direction,

The devices may further include at least one bit line electricallyconnected to the vertical channel regions and extending along a seconddirection perpendicular to the first direction. Top surfaces of theplugs may be located at a level higher than top surfaces of the verticalchannel regions and lower than the at least one bit line and the atleast one strapping line.

In some embodiments, the at least one insulation region may include aplurality of insulation regions disposed between respective adjacentpairs of the gate stacks, and the at least one strapping line mayinclude a plurality of strapping lines, respective ones of which aredisposed on respective ones of the insulation regions, The devices mayfurther include a common source line electrically connected in common tothe plurality of strapping lines. The common source line may be disposedat the same level as the at least one bit line. The devices may alsoinclude a barrier layer conforming to bottom and side surfaces of the atleast one insulation region.

Further embodiments provide methods including forming a mold stackcomprising alternately arranged sacrificial layers and insulating layerson a substrate. Vertical channel regions passing through the mold stackare formed. A trench is formed in the mold stack between adjacent rowsof the vertical channel regions, exposing a portion of the substrate.The trench has a linear first portion of a first width and a widenedsecond portion of a second width greater than the first width. A commonsource region is formed in the exposed portion of the substrate.Portions of the sacrificial layers exposed by the trench are replacedwith conductive material to form a gate stack including alternatelyarranged insulating layers and gate electrode layers. An insulationregion is formed that fills the first portion of the trench, partiallyfills the second portion of the trench and leaves a hole exposing aportion of the common source region. A conductive plug is formed in thehole and connected to the common source region. A strapping line isformed on and in direct electrical contact with the plug. A bit line isformed, electrically connected to at least some of the vertical channelregions.

The methods may further include supplying impurities into an upperportion of the vertical channel to form a drain region before forming ofthe trench. A common source line may be formed simultaneously withforming the bit line using a common material layer.

An interlayer dielectric may be formed on the substrate, covering thestrapping line, and first and second contacts may be formed, passingthrough the interlayer dielectric and electrically contacting respectiveone of a vertical channel region and the strapping line.

In further embodiments, methods include forming a mold stack comprisingalternately arranged sacrificial layers and insulating layers on asubstrate and forming rows of vertical channel regions passing throughthe mold stack. The methods further include forming respective trenchesin the mold stack between adjacent ones of the rows of the verticalchannel regions and exposing portions of the substrate, the trencheseach having linear first portions of a first width and spaced-apartwidened second portions having a second width greater than the firstwidth. Common source regions are formed in the exposed portions of thesubstrate, and respective gate stacks are formed between respectiveadjacent pairs of the trenches from the mold stack. Respectiveinsulation regions are formed in respective ones of the trenches,wherein portions of the insulation regions in the widened secondportions of the trenches have holes therethrough that expose portions ofthe common source regions. Conductive plugs are formed in the holes andconnected to the common source regions. Respective strapping lines areformed on respective ones of the insulation regions and in directelectrical contact with the plugs. A plurality of bit lines is formed,the bit lines crossing the strapping lines and electrically connected tothe vertical channel regions.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingbrief description taken in conjunction with the accompanying drawings.The accompanying drawings represent non-limiting, example embodiments asdescribed herein.

FIGS. 1A and 1B are plan views of a three-dimensional semiconductormemory device according to example embodiments of the subject matter;

FIG. 1C is an equivalent circuit diagram of a three-dimensionalsemiconductor memory device according to example embodiments of thesubject matter;

FIGS. 2A through 10A are sectional views illustrating a method offabricating a three-dimensional semiconductor memory device according toexample embodiments of the subject matter and show vertical sectionstaken along a line A1-A2 of FIG. 1B;

FIGS. 2B through 10B are sectional views illustrating a method offabricating a three-dimensional semiconductor memory device according toexample embodiments of the subject matter and show vertical sectionstaken along a line B1-B2 of FIG. 1B;

FIGS. 11A and 11B are sectional views illustrating a method offabricating a three-dimensional semiconductor memory device according toother example embodiments of the subject matter and shows verticalsections taken along lines A1-A2 and B1-B2, respectively, of FIG. 1B;

FIGS. 12A and 12B are sectional views illustrating a method offabricating a three-dimensional semiconductor memory device according tostill other example embodiments of the subject matter and shows verticalsections taken along lines A1-A2 and B1-B2, respectively, of FIG. 1B;

FIG. 13A is a block diagram of a memory card including athree-dimensional semiconductor memory device according to exampleembodiments of the subject matter; and

FIG. 13B is a block diagram of an information processing systemincluding a three-dimensional semiconductor memory device according toexample embodiments of the subject matter.

It should be noted that these figures are intended to illustrate thegeneral characteristics of methods, structure and/or materials utilizedin certain example embodiments and to supplement the written descriptionprovided below. These drawings are not, however, to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as defining orlimiting the range of values or properties encompassed by exampleembodiments. For example, the relative thicknesses and positioning ofmolecules, layers, regions and/or structural elements may be reduced orexaggerated for clarity. The use of similar or identical referencenumbers in the various drawings is intended to indicate the presence ofa similar or identical element or feature.

DETAILED DESCRIPTION

Example embodiments of the subject matter will now be described morefully with reference to the accompanying drawings, in which exampleembodiments are shown. Example embodiments of the subject matter may,however, be embodied in many different forms and should not be construedas being limited to the embodiments set forth herein; rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the concept of example embodiments tothose of ordinary skill in the art. In the drawings, the thicknesses oflayers and regions are exaggerated for clarity. Like reference numeralsin the drawings denote like elements, and thus their description will beomitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Like numbers indicate like elementsthroughout. As used herein the term “and/or” includes any and allcombinations of one or more of the associated listed items. Other wordsused to describe the relationship between elements or layers should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” “on” versus “directlyon”).

It will be understood that, although the terms “first”, “second”, etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising”, “includes” and/or “including,” if usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Example embodiments of the subject matter are described herein withreference to cross-sectional illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofexample embodiments. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, example embodiments of thesubject matter should not be construed as limited to the particularshapes of regions illustrated herein but are to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle may have rounded or curvedfeatures and/or a gradient of implant concentration at its edges ratherthan a binary change from implanted to non-implanted region. Likewise, aburied region formed by implantation may result in some implantation inthe region between the buried region and the surface through which theimplantation takes place. Thus, the regions illustrated in the figuresare schematic in nature and their shapes are not intended to illustratethe actual shape of a region of a device and are not intended to limitthe scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments of the subjectmatter belong. It will be further understood that terms, such as thosedefined in commonly-used dictionaries, should be interpreted as having ameaning that is consistent with their meaning in the context of therelevant art and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

FIGS. 1A and 1B are plan views of a three-dimensional semiconductormemory device according to example embodiments of the subject matter.Here, FIG. 1B shows some elements selected from FIG. 1A. FIG. 1C is anequivalent circuit diagram of a three-dimensional semiconductor memorydevice according to example embodiments of the subject matter.

Referring to FIGS. 1A and 1B, a semiconductor memory device 1 mayinclude gate stacks 303 disposed on a substrate 300, a plurality of bitlines 395 crossing over the gate stacks 303, at least one common sourceline 396 extending along a direction (e.g., X direction) parallel to thebit lines 395, and a plurality of strapping lines 393 electricallyconnected to the common source line 396. Each of the gate stacks 303 mayinclude a plurality of gates stacked in a vertical direction, and eachcommon source line 396 may be disposed between every N bit lines 395.Each of the strapping lines 393 may be electrically connected to thecommon source line 396 via at least one metal contact 391. In someembodiments, the gate stacks 303 and the strapping lines 393 may besubstantially orthogonal to the bit lines 395 and the common source line396. Each of the strapping lines 393 may be disposed between the gatestacks 303 and extend parallel to the gate stacks 303. The strappinglines 393 may be disposed at a level lower than the bit lines 395, andthe common source line 396 may be disposed at the same level as the bitlines 395. Each of the gate stacks 303 may have a plurality of verticalholes 315 arranged along a direction (e.g., a Y direction) along whichthe gate stacks 303 extend. The semiconductor memory device 1 mayinclude a plurality of vertical channel regions 330, respective ones ofwhich fill respective ones of the vertical holes 315. In someembodiments, the vertical holes 315 and vertical channel regions 330 maybe arranged in a zigzag configuration.

Each of the gate stacks 303 may have sidewalls delimited by trencheshaving portions 345 a and 345 b. Each of the trenches include at leastone line-shaped first trench portion 345 a extending along the Ydirection and having a first width W1 and at least one widened secondtrench portion 345 b having a second width W2 greater than the firstwidth W1. Respective plugs 385 connected to the strapping line 393 maybe provided in the second trench portions 345 b. The second trenchportion 345 b may have a circular, elliptical or polygonal section inplan view, but example embodiments of the subject matter may not belimited thereto. The first and second trench portions 345 a and 345 bmay be formed to partially expose the substrate 300. As shown in FIGS.10A and 10B, common source regions 350 may be formed in portions of thesubstrate 300 exposed by the first and second trench portions 345 a and345 b. The common source region 350 may be a doped region and beelectrically connected to the strapping line 393 via the plugs 385. Aplurality of plugs 385 may be connected to the corresponding one of thestrapping lines 393 and be spaced apart from each other in the Ydirection. The semiconductor memory device 1 may be configured to havevertical sections shown in FIGS. 10A and 10B.

Referring to FIG. 1C in conjunction with FIG. 1B, the bit lines 395 maycorrespond to elements depicted by reference numerals BL0, BL1, BLn ofFIG. 1C, the common source line 396 may correspond to an elementdepicted by a reference numeral CSL of FIG. 1 C. Each of the gate stacks303 may include a ground selection transistor A controlled by a groundselection line GSL, memory transistors B controlled by word lines WL0,WL1, WL2, . . . , WLk, and at least one string selection transistor Ccontrolled by string selection lines SSL0, SSL1, . . . , SSLm. Theground selection transistor A, the memory transistors B and the stringselection transistor C may be vertically stacked along Z direction toshare one vertical channel region 330 which forms their channels,thereby forming a cell string D. Each of the bit lines BL0, BL1, . . . ,BLn may connect a plurality of cell strings D with each other in aparallel manner. In FIG. 1C, parameters m, n and k are integers.

FIGS. 2A through 10A are sectional views illustrating operations forfabricating three-dimensional semiconductor memory devices according toexample embodiments of the subject matter and show vertical sectionstaken along a line A1-A2 of FIG. 1B. FIGS. 2B through 10B are sectionalviews illustrating operations for fabricating a three-dimensionalsemiconductor memory device according to example embodiments of thesubject matter and show vertical sections taken along a line B1-B2 ofFIG. 1B.

Referring to FIGS. 2A and 2B, a mold stack 302 may be formed on thesubstrate 300. The substrate 300 may include a semiconductor material,such as silicon. A well region 301 of a first conductivity type (e.g., ptype) may be formed in the substrate 300. The mold stack 302 may beformed by alternatingly depositing sacrificial layers 305 and insulatinglayers 310 on the substrate 300. The sacrificial layers 305 may beformed of a material having an etch selectivity with respect to theinsulating layers 310. For example, the insulating layers 310 may beformed of oxide (e.g., SiOx) and the sacrificial layers 305 may beformed of nitride (e.g., SiNx). Subsequently, the mold stack 302 may bepatterned to form channel holes 315 exposing the well region 301. Thechannel holes 315 may be formed to have a zigzag configuration, as shownin FIG. 1B, Dotted lines, in FIGS. 2A and 2B, illustrate some of thechannel holes 315 arranged in the zigzag manner.

Referring to FIGS. 3A and 3B, vertical channel regions 330 may be formedto fill the channel holes 315, respectively. In some embodiments, eachof the vertical channel regions 330 may include a semiconductor layer320 and an insulating filler 325. The semiconductor layer 320 may beformed to conformally cover side and bottom surfaces of the channel hole315. For example, the semiconductor layer 320 may have a ‘U’-shapedvertical section. The insulating filler 325 may be formed to fill theremaining space of the channel hole 315, which is not occupied by thesemiconductor layer 320. The vertical channel region 330 may furtherinclude a capping semiconductor layer 327 disposed on the semiconductorlayer 320 and the insulating filler 325. A drain region may be formed byproviding dopants with a second conductivity type (e.g., n type) into anuppermost portion (e.g., the capping semiconductor layer 327) of thevertical channel region 330. The vertical channel regions 330 may bearranged to have the zigzag configuration, as shown in FIG. 1B. Dottedlines, in FIGS. 3A and 3B, illustrate some of the vertical channelregions 330 arranged in the zigzag manner. The semiconductor layer 320and the capping semiconductor layer 327 may include a silicon layer.

Referring to FIGS. 4A and 4B, the mold stack 302 may be patterned toform the trench portions 345 a and 345 b. In some embodiments, aninsulating capping layer 306 may be formed on the mold stack 302, beforethe formation of the trench portions 345 a and 345 b. Each of the trenchportions 345 a and 345 b may be formed to have at least one portion(i.e., the first trench portion 345 a) having the first width W1 and atleast one widened portion (i.e., the second trench portion 345 b) havingthe second width W2 greater than the first width W1. The second trenchportion 345 b may be formed to have a circular, elliptical or polygonalsection in plan view, but example embodiments of the subject matter maynot be limited thereto. In some embodiments, the first and second trenchportions 345 a and 345 b may be formed to have a configuration shown inFIG. 1B. Common source regions 350 may be formed by injecting dopants ofsecond conductivity type (e.g., n-type) into the substrate 300 throughthe first and second trench portions 345 a and 345 b. As a result, thecommon source regions 350 may have a line shape elongated along thefirst trench portion 345 a.

Referring to FIGS. 5A and 5B, the sacrificial layers 305 may beselectively removed to form recesses 355 between the insulating layers310. For example, the formation of the recesses 355 may include etchingthe sacrificial layers 305 exposed by the trench portions 345 a and 345b in a wet etching manner and be performed using an etchant capable ofselectively etching the sacrificial layers 305. For example, in the casein which the sacrificial layers 305 are formed of silicon nitride, theremoval of the sacrificial layers 305 may include supplying an etchingsolution containing phosphoric acid through the first and second trenchportions 345 a and 345 b.

Referring to FIGS. 6A and 6B, memory layers 360 may be conformallyformed over inner walls of the recesses 355, and gates 335 may be formedto fill recess the remaining spaces of the regions 355. As a result, thegates 335 may be vertically stacked on the substrate 300 and constitutethe gate stacks 303. In other words, each of the gate stacks 303 mayinclude a plurality of vertically stacked gates 335, which may be usedas at least one ground selection gate 335 a, at least one stringselection gate 335 c, and a plurality of cell gates 335 b therebetween.In some embodiments, either or both of the ground and string selectiongates 335 a and 335 c may be realized using a plurality of layers (e.g.,two vertically-stacked gates 335). The gate 335 may include, forexample, a doped semiconductor (e.g., dopes silicon), a metal (e.g.,tungsten, copper, and aluminum), a conductive metal nitride (e.g.,titanium nitride and tantalum nitride), and/or a transition metal (e.g.,titanium and tantalum). The memory layer 360 may include a tunnel layer(e.g., of silicon oxide) adjacent to the vertical channel region 330, ablocking layer (e.g., of silicon oxide, aluminum oxide, or hafniumoxide) adjacent to the gate 335, and a trap insulating layer (e.g., ofsilicon nitride) interposed between the tunnel layer and the blockinglayer.

Referring to FIGS. 7A and 7B, insulating trench fillers 378 may beformed in the trench portions 345 a and 345 b. The formation of theinsulating trench fillers 378 may include depositing an insulating layeron the structure provided with the gate stacks 303 and thenanisotropically etching the insulating layer. The insulating layer forthe insulating trench fillers 378 may be conformally deposited to fullyfill the first trench portion 345 a but partially fill the second trenchportion 345 b. As a result, the resulting insulating trench filler 378may be formed to fill fully the first trench portion 345 a as shown inFIG. 7B but to partially fill the second trench portion 345 b as shownin FIG. 7A. In other words, the insulating trench filler 378 may beformed to define a hole 380 in the second trench portion 345 b. In someembodiments, the hole 380 may be formed to expose the common sourceregion 350 and be self-aligned to the common source region 350 or thesecond trench portion 345 b.

Referring to FIGS. 8A and 8B, a conductive layer 385 a may be formed inthe hole 380. In some embodiments, before the formation of theconductive layer 385 a, a barrier layer 383 a may be formed over thecommon source region 350 exposed by the hole 380. For example, thebarrier layer 383 a may be formed by conformally depositing a conductivelayer (e.g., of metal nitride such as titanium nitride or tantalumnitride) and thus conformally cover side and bottom surfaces of the hole380 and a top surface of the gate stack 303. The conductive layer 385 amay be formed of a metal layer (e.g., of tungsten, copper or aluminum)or a transition metal layer (e.g., of titanium or tantalum).

Referring to FIGS. 9A and 9B, the conductive layer 385 a and the barrierlayer 383 a may be planarized using, for example, an etch-back orchemical-mechanical polishing technique to expose the insulating cappinglayer 306. As a result, a barrier 383 with a ‘U’-shaped section may beformed to conformally cover the side and bottom surfaces of the hole380, and a plug 385 may be formed to fill the remaining space of thehole 380. The plug 385 may be electrically connected to the commonsource region 350 in a self-aligned manner. In some embodiments, a topsurface of the plug 385 may be located at level higher than that of thevertical channel region 330.

The strapping line 393 may be formed by depositing and patterning aconductive material. The strapping line 393 may be electricallyconnected to the plug 385. The strapping line 393 may be formed, forexample, from a metal (e.g., tungsten, copper, and aluminum), aconductive metal nitride (e.g., titanium nitride and tantalum nitride)and/or a transition metal (e.g., titanium and tantalum). The strappingline 393 may be patterned to have a line shape extending along thecommon source region 350. The strapping line 393 may be located at alevel higher than the top surface of the vertical channel region 330.

According to some example embodiments of the subject matter, thestrapping line 393 may be connected to the plug 385 without anadditional metal contact plug interposed therebetween. This may allowomission of several process steps of, for example, depositing andetching an additional insulating layer and an additional metal layer,and performing an additional chemical-mechanical polishing process.Furthermore, it is possible to reduce or prevent technical problemsaccompanied by the formation of the additional metal contact plug fromoccurring. For example, it is possible to reduce the likelihood offormation of a void in the insulating trench filler 378 and to thusreduce the likelihood of an electric short circuit between the stringselection gate 335 c and the barrier 383 or between the string selectiongate 335 c and the plug 385.

Referring to FIGS. 10A and 10B, an interlayer dielectric 388 may beformed on the substrate 300, and respective metal contacts 390 may beformed through the interlayer dielectric 388 and the capping layer 306,connecting to respective ones of the vertical channel regions 330. Bitlines 395 may be formed on the interlayer dielectric 395, electricallyconnected to the vertical channel regions 330 via the metal contacts390. The bit lines 395 may be formed, for example, from a metal (e.g.,tungsten, copper, and aluminum), a conductive metal nitride (e.g.,titanium nitride and tantalum nitride) and/or a transition metal (e.g.,titanium and tantalum). Bit lines 395 may be formed at a level higherthan a top surface of the plug 385 and the strapping line 393 and extendalong a direction crossing the strapping line 393. In addition, secondmetal contacts 391 may be formed through the interlayer dielectric 388,and a common source line 396 shown in FIG. 1A may be formed, connectedto the second metal contact 391. The second metal contact 391 may becoupled to the strapping line 393 and may electrically connect thestrapping line 393 to the common source line 396. The second metalcontact 391 and the metal contact 390 may be simultaneously formed usingthe same process, and the common source line 396 and the bit lines 395may be simultaneously formed using the same process.

FIGS. 11A and 11B are sectional views illustrating operations forfabricating a three-dimensional semiconductor memory device according tofurther example embodiments of the subject matter, and FIGS. 12A and 12Bare sectional views illustrating operations for fabricating athree-dimensional semiconductor memory device according to still otherexample embodiments of the subject matter. FIGS. 11A and 12A showsvertical sections taken along a line A1-A2 of FIG. 1B, and FIGS. 11B and12B shows vertical sections taken along a line B1-B2 of FIG. 1B.

Referring to FIGS. 11A and 11B, a spacer layer 372 may be formed onsidewalls of the gate stack 303. A metal-semiconductor compound layer375 (such as CoSix) may be formed on a top surface of the common sourceregion 350. The metal-semiconductor compound layer 375 may be formed ina region delimited by the spacer layer 372. The formation of the memorylayer 360 may include forming a first layer 360 a surrounding the gates335 a, 335 b and 335 c and a second layer 360 b vertically extendingalong a sidewall of the vertical channel region 330. The first layer 360a may include the tunnel layer, and the second layer 360 b may includethe blocking layer. One of the first and second layers 360 a and 360 bmay further include a trap insulating layer.

Referring to FIGS. 12A and 12B, according to the present embodiments,the memory layer 360 may be formed to vertically extend along a sidewallof the vertical channel region 330. For example, the gates 335 a, 335 band 335 c may be formed in direct contact with a top or bottom surfaceof the insulating layers 310. This may allow an increase in verticalthicknesses of the gates 335 a, 335 b and 335 c or a reduction of avertical thickness of the gate stack 303.

FIG. 13A is a block diagram of a memory card including athree-dimensional semiconductor memory device according to exampleembodiments of the subject matter. Referring to FIG. 13A, a memory card1200 may include a memory controller 1220 controlling general dataexchanges between a host and the memory device 1210. A static randomaccess memory (SRAM) 1221 may be used as an operating memory of aprocessing unit 1222. A host interface 1223 may include a data exchangeprotocol of a host connected to a memory card 1200. An error correctionblock 1224 may detect and correct errors included in data read from amulti-bit memory device 1210. A memory interface 1225 may interface withthe memory device 1210. A processing unit 1222 may perform generalcontrol operations for data exchange of the memory controller 1220. Thememory card 1200 may be realized using a memory device 1210 includingthe three-dimensional semiconductor memory devices 1 according toexample embodiments of the subject matter.

FIG. 13B is a block diagram of an information processing systemincluding a three-dimensional semiconductor memory device according toexample embodiments of the subject matter. Referring to FIG. 13B, aninformation processing system 1300 may be realized using a memory system1310 including the three-dimensional semiconductor memory device 1according to example embodiments of the subject matter. For instance,the information processing system 1300 may be a mobile device and/or adesktop computer. In some embodiments, the information processing system1300 may further include a modem 1320, a central processing unit (CPU)1330, a random access memory (RAM) 1340, and a user interface 1350,which are electrically connected to a system bus 1360, in addition tothe memory system 1310. The memory system 1310 may include a memorydevice 1311 and a memory controller 1312. In some embodiments, thememory system 1310 may be configured substantially identical to thememory card 1200 described with respect to FIG. 13A. Data processed bythe CPU 1330 and/or input from the outside may be stored in the memorysystem 1310. In some embodiments, the memory system 1310 may be used asa portion of a solid state drive (SSD), and in this case, theinformation processing system 1300 may stably and reliably store a largeamount of data in the memory system 1310. Although not illustrated, itis apparent to those skilled in the art that, for example, anapplication chipset, a camera image sensor, a camera image signalprocessor (ISP), an input/output device, or the like may further beincluded in the information processing system 1300 according to thesubject matter.

According to some example embodiments of the subject matter, a plug maybe connected to a common source region, and a strapping line may beelectrically connected to the plug without additional metal contact pluginterposed therebetween. Accordingly, it is possible to omit severalprocess steps for forming the additional metal contact plug and/or toreduce or prevent technical problems accompanied by the formation of theadditional metal contact plug from occurring. As a result, it ispossible to realize a semiconductor memory device with improved electricreliability.

While some example embodiments of the subject matter have beenparticularly shown and described, it will be understood by one ofordinary skill in the art that variations in form and detail may be madetherein without departing from the spirit and scope of the attachedclaims.

What is claimed is:
 1. A method comprising: forming a mold stackcomprising alternately arranged sacrificial layers and insulating layerson a substrate; forming a plurality of vertical channel regions passingthrough the mold stack; forming a trench passing through the mold stackbetween adjacent rows of the vertical channel regions and exposing aportion of the substrate, the trench having a linear first portion of afirst width and a widened second portion of a second width greater thanthe first width; forming a common source region in the exposed portionof the substrate; replacing portions of the sacrificial layers exposedby the trench with conductive material to form a gate stack includingalternately arranged insulating layers and gate electrode layers;forming an insulation region that fills the first portion of the trench,partially fills the second portion of the trench and leaves a holeexposing a portion of the common source region; forming a conductiveplug in the hole and connected to the common source region; forming astrapping line on and in direct electrical contact with the plug; andforming a bit line electrically connected to at least some of thevertical channel regions.
 2. The method of claim 1, further comprisingsupplying impurities into an upper portion of the vertical channelregion to form a drain region before forming of the trench.
 3. Themethod of claim 1, further comprising forming a common source linesimultaneously with forming the bit line using a common material layer.4. The method of claim 3, further comprising: forming an interlayerdielectric on the substrate, covering the strapping line; and formingfirst and second contacts passing through the interlayer dielectric andelectrically contacting respective one of a vertical channel region andthe strapping line.
 5. The method of claim 3, wherein the strapping lineextends in parallel with the trench, and wherein the common source lineand the bit line cross the strapping line.
 6. A method comprising:forming a mold stack comprising alternately arranged sacrificial layersand insulating layers on a substrate; forming rows of vertical channelregions passing through the mold stack; forming respective trenches inthe mold stack between adjacent ones of the rows of the vertical channelregions and exposing portions of the substrate, the trenches each havinglinear first portions of a first width and spaced-apart widened secondportions having a second width greater than the first width; formingcommon source regions in the exposed portions of the substrate; formingrespective gate stacks between respective adjacent pairs of the trenchesfrom the mold stack; forming respective insulation regions in respectiveones of the trenches, wherein portions of the insulation regions in thewidened second portions of the trenches have holes therethrough thatexpose portions of the common source regions; forming conductive plugsin the holes and connected to the common source regions; formingrespective strapping lines on respective ones of the insulation regionsand in direct electrical contact with the plugs; and forming a pluralityof bit lines crossing the strapping lines and electrically connected tothe vertical channel regions.
 7. The method of claim 6, furthercomprising supplying impurities into upper portions of the verticalchannel regions to form drain regions before forming of the trenches. 8.The method of claim 6, further comprising forming a common source linesimultaneously with forming the bit lines using a common material layer.9. The method of claim 8, wherein the strapping lines extend in parallelwith the trenches, and wherein the common source line and the hit linescross the strapping lines.
 10. The method of claim 6, furthercomprising: forming an interlayer dielectric on the substrate, coveringthe strapping lines; and forming contacts passing through the interlayerdielectric and electrically contacting respective ones of the verticalchannel regions and the strapping lines.
 11. The method of claim 6,further comprising forming barrier layers in the second portions of thetrenches before forming the plugs.
 12. The method of claim 6, whereinforming respective gate stacks between respective adjacent pairs of thetrenches from the mold stack comprises replacing portions of thesacrificial layers exposed by the trenches with conductive material toform the gate stacks.